Junior ASIC/FPGA Design Engineer
- Position Title - Junior ASIC/FPGA Design Engineer
- Salary Range - Competitive - D.O.E.
- Work Type - Full-Time
- Desired Start Date - Immediately
- Job Location(s) - San Jose, CA or Portland, OR
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Candidates for this position will be expected to be able to design, implement and test both unit level modules and higher level architecture designs. This role requires candidates to develop RTL and synthesize it onto an FPGA for testing. In addition candidates will be creating and implementing test plans for validating the design.
cPacket Networks offers a Next Generation Network Monitoring Architecture that allows Network Operators to achieve up to 80% faster troubleshooting Mean Time to Resolution (MTTR) over standard legacy network monitoring tools. This distributed solution combines proactive network visibility, granular packet-based analytics, real-time search across L2-L7, and forensic storage, for unmatched integrated Operational Intelligence. By improving operational efficiency, customers can achieve considerable OpEx and CapEx savings. Based in Silicon Valley, CA, our solutions are relied on to troubleshoot some of the world’s largest network infrastructures.