ASIC/FPGA Verification Engineer (UVM)
- Position Title - ASIC/FPGA Verification Engineer (UVM)
- Salary Range - Competitive - D.O.E.
- Work Type - Full-Time
- Desired Start Date - Immediately
- Job Location(s) - San Jose, CA or Portland, OR
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This role will require candidates to develop and integrate the current and future RTL designs into a UVM environment. Candidates will need to create reports providing coverage and testing results to the teams to help troubleshoot issues in the design. This role may also require creating behavioral models of the design and developing RTL which will be integrated into the testing environment.
cPacket Networks offers a Next Generation Network Monitoring Architecture that allows Network Operators to achieve up to 80% faster troubleshooting Mean Time to Resolution (MTTR) over standard legacy network monitoring tools. This distributed solution combines proactive network visibility, granular packet-based analytics, real-time search across L2-L7, and forensic storage, for unmatched integrated Operational Intelligence. By improving operational efficiency, customers can achieve considerable OpEx and CapEx savings. Based in Silicon Valley, CA, our solutions are relied on to troubleshoot some of the world’s largest network infrastructures.